This invention pertains to digital-to-analog converter circuits. More particularly, this invention relates to integrated circuits which employ the summing of binary weighted currents to effect digital-to-analog conversion.
Binary weighted digital-to-analog converters (DACs) are well known in the art and many circuit implementations have been provided to satisfy various requirements. One type of prior art circuit comprises a plurality of parallel connected current sources and a current summing network wherein each current source is responsive to a particular signal bit of an applied digital signal and supplies a binary weighted current to the summing network, i.e., the currents supplied to the summing network in response to successive bits of the digital input signal vary by a factor of 2. Most binary weighted DACs of this type include current sources which are transistors connected in a common base configuration with the emitter electrodes connected to the individual legs or rungs of an R-2R ladder network. Because each current source transistor of such a converter operates with a different collector current, each current source transistor exhibits a different base-to-emitter voltage (V.sub.BE). Such a variation in V.sub.BE, in turn, causes the potential across each leg of the R-2R ladder network to deviate from that potential which would be induced solely by the respective binary weighted current source, thus introducing errors in the analog output signal.
In the above-described prior art integrated binary weighted DACs, the base electrodes of the current source transistors are commonly connected to a voltage source and, to equalize the V.sub.BE 's of the current source transistors, the current source transistor emitter areas are generally scaled according to the magnitude of the binary weighted current to be generated. This technique maintains a relatively constant current density in the emitter region of each current source transistor and thereby maintains the V.sub.BE of all current source transistors substantially equal.
Emitter area scaling, however, has at least two distinct limitations. First, it is extremely difficult to control the photomask process utilized in the manufacture of integrated circuits to that degree necessary to maintain the required scaling accuracies. Secondly, since the emitter areas are necessarily related to one another in a binary fashion, the emitter area of the current source generating the largest current can become extremely large. For example, in an 8-bit DAC, the emitter area of the current source associated with the most significant bit of the digital input signal must be 128 times as large as the emitter area of the current source associated with the least significant bit. This requires a great deal of area on the silicon chip and is subject to integrated circuit photoprocessing limitations.
It is accordingly an object of this invention to provide an integrated circuit binary weighted DAC which maintains the emitter electrodes of the current source transistors at substantially equal voltages without requiring emitter area scaling.